1. Field of the Invention
The present invention relates generally to circuitry used for the purpose of voltage regulation. Specifically, the present invention relates to a circuit for deriving a reference voltage signal from a system voltage source and for regulating the reference voltage signal so that it remains substantially unaffected by variations in the system voltage level, temperature of the environment, and processing related variations of circuit components.
2. Description of the Prior Art
Typically, an electronic system includes a system voltage source providing a system voltage level V.sub.dd for its electronic sub-systems. Some electronic subsystems require voltage sources which provide particularly stable voltage levels not equal to the system voltage level Vdd. For example, solid state memory storage systems, such as flash memory components used in a portable computer, suffer in performance when the reference voltage is not maintained within predefined tolerance levels.
There exists in the prior art a variety of methods and circuit devices for deriving a reference voltage signal from a system voltage source. There also exists a variety of methods and circuit devices for regulating voltage levels.
FIG. 1 shows a schematic diagram of an exemplary prior art voltage regulator circuit 10. Circuit 10 comprises: a system voltage source 12; a voltage divider including a first resistor 14 having one terminal connected to voltage source 12 and an opposite terminal connected to a node 16, and a second resistor 18 having one terminal connected to ground and an opposite terminal connected to node 16; an operational amplifier (OP-Amp) 20 having a reference input 22 connected to node 16, a feedback input 24, a power input 28 connected to system voltage source 12, and an output 26; a bipolar transistor 40 having its base 42 connected to output 26, its emitter 44 connected to system voltage source 12, and its collector 46 connected to a node 47; a load resistor 50 having one terminal connected to a node 48 and an opposite terminal connected to ground; and a capacitor 52 having one terminal connected to node 48 and an opposite terminal connected to ground. Circuit 10 generates an output reference voltage V.sub.r across terminals 47 and 48. Feedback input 24 of Op-Amp 20 is connected to terminal 48. A switch 54 selectively connects terminals 47 and 48.
The voltage divider is responsive to system voltage source 12 to generate a source reference voltage level V.sub.ref at node 16. Op-Amp 20 is responsive to the source reference voltage level V.sub.ref received at input 22 and the output voltage reference level V.sub.r received at feedback input 24 to generate an output voltage level V.sub.O at its output 26 wherein voltage level V.sub.O which is proportional to the difference between the source reference voltage level V.sub.ref and the output reference voltage level V.sub.R. The output voltage level V.sub.O is increased when V.sub.ref &lt;V.sub.R and is decreased when V.sub.ref &gt;V.sub.R.
Transistor 40 is a p-n-p type bipolar transistor and in the active mode, the collector current I.sub.C through transistor 40 increases as the positive bias V.sub.O across the base junction of transistor 40 is decreased.
When V.sub.ref =V.sub.r, the output voltage level V.sub.O provided at output 26 of the Op-Amp 20 is at a threshold level, transistor 40 is in the active region, and the output reference voltage level V.sub.r across nodes 47 and 48 for example is at 3.3 volts. If the system voltage level V.sub.dd, increases due to a power supply variation, then the output voltage reference level V.sub.r generated at the output terminal is increased. In response, the output voltage level V.sub.O provided at output 26 of the Op-Amp 20 increases causing a decrease in the collector current I.sub.C through transistor 40; and a decrease in the output voltage reference level V.sub.r to compensate for the increase in V.sub.dd.
If the system voltage level V.sub.dd decreases, then the output voltage reference level V.sub.r generated at the output terminal is decreased. In response, the voltage level V.sub.O provided at output 26 of the Op-Amp decreases causing an increase in the collector current I.sub.C through transistor 40 and an increase in the output voltage reference level V.sub.r to compensate for the decrease in V.sub.dd. The problem with this technique is that fluctuations in V.sub.dd change Vref due to the proportionality between V.sub.ref and V.sub.dd. This causes V.sub.r to follow the changes in V.sub.dd. As an example, if V.sub.dd drops by 10%, Vref will also drop by 10%, as does V.sub.r.
In general, fluctuations in the system voltage level V.sub.dd may result from power supply variances and other like affects. Fluctuations in the reference voltage level generated by a reference generator often arise due to variations in temperature of the environment. For example, temperature variations in the environment of an electronic system may range from 0.degree. C. to 95.degree. C. Fluctuations in the reference voltage level may also arise due to processing related variations of the circuit components of the reference generator. Reference generator circuitry implemented using complementary metal oxide semiconductor (CMOS) technology is particularly susceptible to voltage fluctuations caused by process related variations of the circuit components of the reference generator. This is partly due to the fact that N-channel and P-channel transistors are known to operate differently under varying temperatures.
FIG. 1a shows an application of the prior art voltage generator and regulator circuit 10 of FIG. 1. This application in particular relates to a solid state storage system 324, which includes a controller 310, a voltage regulator and generator circuit 312 and a flash memory unit 322. The controller 310 controls the operation of and supplies power to the flash memory unit 322. In so doing, the controller 310 supplies a V.sub.r signal (generally at 3.3V) to the flash unit 322 through the use of the regulator circuit 312. The latter is similar in operation to the prior art circuit shown in FIG. 1 herein. In FIG. 1a, the regulator circuit 312 is shown to reside, in part, within the controller and in part, outside of the controller 310.
Specifically, the transistor 40 and capacitor 52 of the circuit 10 of FIG. 1 are shown included in the regulator circuit 312 but residing outside of the controller 310. These components occupy space on, for example, a card upon which the system 312 may be placed.
What is needed is a circuit for deriving a reference signal having a reference voltage from a system voltage source having a system voltage level V.sub.dd and for regulating the reference signal such that the reference voltage level remains substantially unaffected by variations in the system voltage level V.sub.dd and current load.
What is also needed is such a circuit wherein complementary metal oxide semiconductor (CMOS) technology is used to implement the circuit.
What is further needed is such a circuit wherein the voltage level of the reference signal remains substantially unaffected by variations in the behavior of components of the circuit due to processing characteristics and temperature characteristics of the components.